1. Field of the Invention
The present invention relates generally to phase detection circuits and more specifically to synchronous phase detection circuits for detecting phase relationships between clock signals having either an integer multiple, n:1, or a 3:2 (meaning three period of the high-frequency clock for every 2 periods of the low-frequency clock) frequency relationship.
2. Prior Art
Today's microprocessors and computers utilize multiple buses and functional logic blocks that may operate at different frequencies. To facilitate the transfer of data between units operating at different frequencies, it is helpful to know the phase relationship between the clocks of the individual units. For example, a first state machine may operate at 66 MHz and a second state machine at 33 MHz. After sending a request to the second state machine, the first state machine must know when the second state machine has taken the request. Suppose that the first state machine knows that the second state machine will take a request on the first rising-edge of its clock after receiving the request. In this case, detecting when the rising-edges of the lower frequency clock occur with respect to the higher frequency clock allows the first state machine to know when the request will be taken by the second state machine.
Asynchronous phase detection circuits for detecting phase relationships between clocks having a 2:1 frequency relationship are known. An asynchronous phase detector circuit for detecting the phase relationship between a high-frequency clock that is twice the frequency of a low-frequency clock uses an asynchronous delay unit and a D flip-flop. The asynchronous delay unit, which is typically a chain of inverters, receives the low-frequency clock as an input and generates a delayed low-frequency clock signal. The D flip-flop receives the delayed low-frequency clock signal at its D input and the high-frequency clock at its clock input such that on a rising-edge of the high-frequency clock, the delayed low-frequency clock is sampled to create a sampled delayed low-frequency clock signal at the Q output of the D flip-flop. In the case of a 2:1 frequency relationship, a falling-edge on the sampled delayed low-frequency clock signal indicates that a rising-edge of the high-frequency clock corresponds to a rising-edge of the low-frequency clock.
Two problems with this asynchronous phase detector circuit are: 1) it does not generalize to any integer multiple frequency relationship between the low and high frequency clocks and 2) substantial control of the amount of delay inserted by the asynchronous delay unit is required. The second problem involves controlling the asynchronous delay such that the delayed low frequency signal meets the setup-time and hold-time requirements of the D flip-flop. The asynchronous delay must meet these timing requirements when the circuit is operated over specified temperature and voltage ranges taking into account the process variations in manufacturing the delay circuit.
Attaining sufficient control of the amount of asynchronous delay becomes more difficult at higher clock frequencies. This fact highlights the delay control problem because the steady trend in the electronics industry is to increase the clock speeds of electronic devices in order to satisfy the demand for increased performance. This is especially true for microprocessors and computers.
In addition, since microprocessors and computers are synchronous machines, a synchronous phase detection circuit would be the most straightforward implementation for use in microprocessors and computer systems.
Therefore, a method and apparatus for synchronously detecting phase relationships between a low-frequency and a high-frequency clock is needed.